###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

set_property PACKAGE_PIN G24 [get_ports {ddr4_rtl_1_adr[0]}]
set_property PACKAGE_PIN G25 [get_ports {ddr4_rtl_1_adr[1]}]
set_property PACKAGE_PIN G20 [get_ports {ddr4_rtl_1_adr[2]}]
set_property PACKAGE_PIN G21 [get_ports {ddr4_rtl_1_adr[3]}]
set_property PACKAGE_PIN J24 [get_ports {ddr4_rtl_1_adr[4]}]
set_property PACKAGE_PIN H24 [get_ports {ddr4_rtl_1_adr[5]}]
set_property PACKAGE_PIN J21 [get_ports {ddr4_rtl_1_adr[6]}]
set_property PACKAGE_PIN H21 [get_ports {ddr4_rtl_1_adr[7]}]
set_property PACKAGE_PIN J22 [get_ports {ddr4_rtl_1_adr[8]}]
set_property PACKAGE_PIN H22 [get_ports {ddr4_rtl_1_adr[9]}]
set_property PACKAGE_PIN J20 [get_ports {ddr4_rtl_1_adr[10]}]
set_property PACKAGE_PIN N21 [get_ports {ddr4_rtl_1_adr[11]}]
set_property PACKAGE_PIN M21 [get_ports {ddr4_rtl_1_adr[12]}]
set_property PACKAGE_PIN K23 [get_ports {ddr4_rtl_1_adr[13]}]
set_property PACKAGE_PIN K24 [get_ports {ddr4_rtl_1_adr[14]}]
set_property PACKAGE_PIN L21 [get_ports {ddr4_rtl_1_adr[15]}]
set_property PACKAGE_PIN M20 [get_ports {ddr4_rtl_1_adr[16]}]
set_property PACKAGE_PIN E20 [get_ports {ddr4_rtl_1_dq[0]}]
set_property PACKAGE_PIN D16 [get_ports {ddr4_rtl_1_dq[1]}]
set_property PACKAGE_PIN G18 [get_ports {ddr4_rtl_1_dq[2]}]
set_property PACKAGE_PIN E17 [get_ports {ddr4_rtl_1_dq[3]}]
set_property PACKAGE_PIN G19 [get_ports {ddr4_rtl_1_dq[4]}]
set_property PACKAGE_PIN F18 [get_ports {ddr4_rtl_1_dq[5]}]
set_property PACKAGE_PIN F20 [get_ports {ddr4_rtl_1_dq[6]}]
set_property PACKAGE_PIN D17 [get_ports {ddr4_rtl_1_dq[7]}]
set_property PACKAGE_PIN B19 [get_ports {ddr4_rtl_1_dq[8]}]
set_property PACKAGE_PIN A16 [get_ports {ddr4_rtl_1_dq[9]}]
set_property PACKAGE_PIN B20 [get_ports {ddr4_rtl_1_dq[10]}]
set_property PACKAGE_PIN C17 [get_ports {ddr4_rtl_1_dq[11]}]
set_property PACKAGE_PIN A20 [get_ports {ddr4_rtl_1_dq[12]}]
set_property PACKAGE_PIN B16 [get_ports {ddr4_rtl_1_dq[13]}]
set_property PACKAGE_PIN B18 [get_ports {ddr4_rtl_1_dq[14]}]
set_property PACKAGE_PIN C16 [get_ports {ddr4_rtl_1_dq[15]}]
set_property PACKAGE_PIN B25 [get_ports {ddr4_rtl_1_dq[16]}]
set_property PACKAGE_PIN C21 [get_ports {ddr4_rtl_1_dq[17]}]
set_property PACKAGE_PIN B24 [get_ports {ddr4_rtl_1_dq[18]}]
set_property PACKAGE_PIN C22 [get_ports {ddr4_rtl_1_dq[19]}]
set_property PACKAGE_PIN B26 [get_ports {ddr4_rtl_1_dq[20]}]
set_property PACKAGE_PIN A21 [get_ports {ddr4_rtl_1_dq[21]}]
set_property PACKAGE_PIN B21 [get_ports {ddr4_rtl_1_dq[23]}]
set_property PACKAGE_PIN B23 [get_ports {ddr4_rtl_1_dq[22]}]
set_property PACKAGE_PIN E23 [get_ports {ddr4_rtl_1_dq[24]}]
set_property PACKAGE_PIN F21 [get_ports {ddr4_rtl_1_dq[25]}]
set_property PACKAGE_PIN F23 [get_ports {ddr4_rtl_1_dq[26]}]
set_property PACKAGE_PIN F22 [get_ports {ddr4_rtl_1_dq[27]}]
set_property PACKAGE_PIN E25 [get_ports {ddr4_rtl_1_dq[28]}]
set_property PACKAGE_PIN D22 [get_ports {ddr4_rtl_1_dq[29]}]
set_property PACKAGE_PIN F25 [get_ports {ddr4_rtl_1_dq[30]}]
set_property PACKAGE_PIN D21 [get_ports {ddr4_rtl_1_dq[31]}]
set_property PACKAGE_PIN E19 [get_ports {ddr4_rtl_1_dqs_t[0]}]
set_property PACKAGE_PIN A18 [get_ports {ddr4_rtl_1_dqs_t[1]}]
set_property PACKAGE_PIN A25 [get_ports {ddr4_rtl_1_dqs_t[2]}]
set_property PACKAGE_PIN D24 [get_ports {ddr4_rtl_1_dqs_t[3]}]
set_property PACKAGE_PIN L22 [get_ports {ddr4_rtl_1_ba[0]}]
set_property PACKAGE_PIN L23 [get_ports {ddr4_rtl_1_ba[1]}]
set_property PACKAGE_PIN L20 [get_ports {ddr4_rtl_1_bg[0]}]
set_property PACKAGE_PIN N22 [get_ports {ddr4_rtl_1_ck_t[0]}]
set_property PACKAGE_PIN D25 [get_ports {ddr4_rtl_1_odt[0]}]
set_property PACKAGE_PIN F17 [get_ports {ddr4_rtl_1_dm_n[0]}]
set_property PACKAGE_PIN C19 [get_ports {ddr4_rtl_1_dm_n[1]}]
set_property PACKAGE_PIN A22 [get_ports {ddr4_rtl_1_dm_n[2]}]
set_property PACKAGE_PIN E24 [get_ports {ddr4_rtl_1_dm_n[3]}]
set_property PACKAGE_PIN A23 [get_ports {ddr4_rtl_1_cs_n[0]}]
set_property PACKAGE_PIN E22 [get_ports ddr4_rtl_1_act_n]
set_property PACKAGE_PIN K22 [get_ports {ddr4_rtl_1_cke[0]}]
set_property PACKAGE_PIN D20 [get_ports ddr4_rtl_1_reset_n]

set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVDS} [get_ports ddr4_ref_1_clk_p]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_par]
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_alert_n]

set_property PACKAGE_PIN N12    [get_ports ref_clk_a_p];
set_property PACKAGE_PIN N11    [get_ports ref_clk_a_n];

set_property PACKAGE_PIN D2 [get_ports {rx_data_a_p[0]}]
set_property PACKAGE_PIN D1 [get_ports {rx_data_a_n[0]}]
set_property PACKAGE_PIN D6 [get_ports {tx_data_a_p[0]}]
set_property PACKAGE_PIN D5 [get_ports {tx_data_a_n[0]}]
set_property PACKAGE_PIN C4 [get_ports {rx_data_a_p[1]}]
set_property PACKAGE_PIN C3 [get_ports {rx_data_a_n[1]}]
set_property PACKAGE_PIN C8 [get_ports {tx_data_a_p[1]}]
set_property PACKAGE_PIN C7 [get_ports {tx_data_a_n[1]}]
set_property PACKAGE_PIN B2 [get_ports {rx_data_a_p[2]}]
set_property PACKAGE_PIN B1 [get_ports {rx_data_a_n[2]}]
set_property PACKAGE_PIN B6 [get_ports {tx_data_a_p[2]}]
set_property PACKAGE_PIN B5 [get_ports {tx_data_a_n[2]}]
set_property PACKAGE_PIN A4 [get_ports {rx_data_a_p[3]}]
set_property PACKAGE_PIN A3 [get_ports {rx_data_a_n[3]}]
set_property PACKAGE_PIN A8 [get_ports {tx_data_a_p[3]}]
set_property PACKAGE_PIN A7 [get_ports {tx_data_a_n[3]}]

set_property PACKAGE_PIN R12 [get_ports ref_clk_b_p]
set_property PACKAGE_PIN R11 [get_ports ref_clk_b_n]

set_property PACKAGE_PIN H2 [get_ports {rx_data_b_p[0]}]
set_property PACKAGE_PIN H1 [get_ports {rx_data_b_n[0]}]
set_property PACKAGE_PIN H6 [get_ports {tx_data_b_p[0]}]
set_property PACKAGE_PIN H5 [get_ports {tx_data_b_n[0]}]
set_property PACKAGE_PIN G4 [get_ports {rx_data_b_p[1]}]
set_property PACKAGE_PIN G3 [get_ports {rx_data_b_n[1]}]
set_property PACKAGE_PIN G8 [get_ports {tx_data_b_p[1]}]
set_property PACKAGE_PIN G7 [get_ports {tx_data_b_n[1]}]
set_property PACKAGE_PIN F2 [get_ports {rx_data_b_p[2]}]
set_property PACKAGE_PIN F1 [get_ports {rx_data_b_n[2]}]
set_property PACKAGE_PIN F6 [get_ports {tx_data_b_p[2]}]
set_property PACKAGE_PIN F5 [get_ports {tx_data_b_n[2]}]
set_property PACKAGE_PIN E4 [get_ports {rx_data_b_p[3]}]
set_property PACKAGE_PIN E3 [get_ports {rx_data_b_n[3]}]
set_property PACKAGE_PIN E8 [get_ports {tx_data_b_p[3]}]
set_property PACKAGE_PIN E7 [get_ports {tx_data_b_n[3]}]

# Core clocks (BANK 66, can be used other clock pins from the bank)
set_property -dict {PACKAGE_PIN AU6  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}   [get_ports core_clk_a_p]
set_property -dict {PACKAGE_PIN AV6  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}   [get_ports core_clk_a_n]
set_property -dict {PACKAGE_PIN AV8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}   [get_ports core_clk_b_p]
set_property -dict {PACKAGE_PIN AV7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}   [get_ports core_clk_b_n]

set_property -dict {PACKAGE_PIN AT2  IOSTANDARD LVDS} [get_ports rx_sync_a_n]
set_property -dict {PACKAGE_PIN AR2  IOSTANDARD LVDS} [get_ports rx_sync_a_p]
set_property -dict {PACKAGE_PIN AT18 IOSTANDARD LVDS} [get_ports rx_os_sync_a_n]
set_property -dict {PACKAGE_PIN AR18 IOSTANDARD LVDS} [get_ports rx_os_sync_a_p]
set_property -dict {PACKAGE_PIN AV3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_n]
set_property -dict {PACKAGE_PIN AU3  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_p]
set_property -dict {PACKAGE_PIN AW2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_1_n]
set_property -dict {PACKAGE_PIN AV2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_1_p]
set_property -dict {PACKAGE_PIN AU1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_a_n]
set_property -dict {PACKAGE_PIN AT1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_a_p]

set_property -dict {PACKAGE_PIN AR3  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_a]
set_property -dict {PACKAGE_PIN AT3  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_a]
set_property -dict {PACKAGE_PIN AP2  IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_a]
set_property -dict {PACKAGE_PIN AP1  IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_a]
set_property -dict {PACKAGE_PIN AL11 IOSTANDARD LVCMOS18} [get_ports adrv9009_test_a]
set_property -dict {PACKAGE_PIN AV9  IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_a]
set_property -dict {PACKAGE_PIN AW9  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_a]
set_property -dict {PACKAGE_PIN AW7  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_a]
set_property -dict {PACKAGE_PIN AW6  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_a]
set_property -dict {PACKAGE_PIN AU5  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_a]
set_property -dict {PACKAGE_PIN AU4  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_a]
set_property -dict {PACKAGE_PIN AV4  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_a]
set_property -dict {PACKAGE_PIN AW4  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_a]
set_property -dict {PACKAGE_PIN AT8  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_a]
set_property -dict {PACKAGE_PIN AT7  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_a]
set_property -dict {PACKAGE_PIN AT6  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15_a]
set_property -dict {PACKAGE_PIN AT5  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_a]
set_property -dict {PACKAGE_PIN AU9  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09_a]
set_property -dict {PACKAGE_PIN AU8  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10_a]
set_property -dict {PACKAGE_PIN AR5  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11_a]
set_property -dict {PACKAGE_PIN AR4  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12_a]
set_property -dict {PACKAGE_PIN AP7  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14_a]
set_property -dict {PACKAGE_PIN AR7  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13_a]
set_property -dict {PACKAGE_PIN AP5  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17_a]
set_property -dict {PACKAGE_PIN AP4  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16_a]
set_property -dict {PACKAGE_PIN AP6  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18_a]

set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS} [get_ports rx_sync_b_n]
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS} [get_ports rx_sync_b_p]
set_property -dict {PACKAGE_PIN AT16 IOSTANDARD LVDS} [get_ports rx_os_sync_b_n]
set_property -dict {PACKAGE_PIN AT17 IOSTANDARD LVDS} [get_ports rx_os_sync_b_p]
set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_n]
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_p]
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_1_n]
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_1_p]
set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_b_n]
set_property -dict {PACKAGE_PIN AP11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_b_p]

set_property -dict {PACKAGE_PIN AW5  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_b]
set_property -dict {PACKAGE_PIN AR8  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_b]
set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_b]
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_b]
set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS18} [get_ports adrv9009_test_b]
set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_b]
set_property -dict {PACKAGE_PIN AK10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_b]
set_property -dict {PACKAGE_PIN AM11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_b]
set_property -dict {PACKAGE_PIN AN11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_b]
set_property -dict {PACKAGE_PIN AU18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_b]
set_property -dict {PACKAGE_PIN AV18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_b]
set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_b]
set_property -dict {PACKAGE_PIN AW21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_b]
set_property -dict {PACKAGE_PIN AV17 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_b]
set_property -dict {PACKAGE_PIN AW17 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_b]
set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15_b]
set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_b]
set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09_b]
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10_b]
set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11_b]
set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12_b]
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14_b]
set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13_b]
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17_b]
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16_b]
set_property -dict {PACKAGE_PIN AL10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18_b]

set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS18} [get_ports hmc7044_reset]
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18} [get_ports hmc7044_sync]
set_property -dict {PACKAGE_PIN AK19 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_1]
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_2]
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_3]
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_4]

set_property -dict {PACKAGE_PIN AL18 IOSTANDARD LVCMOS18}  [get_ports spi_csn_adrv9009_a]
set_property -dict {PACKAGE_PIN AL17 IOSTANDARD LVCMOS18}  [get_ports spi_csn_adrv9009_b]
set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVCMOS18}  [get_ports spi_csn_hmc7044]

create_clock -name tx_dev_clk        -period  4.00 [get_ports core_clk_a_p]
create_clock -name rx_dev_clk        -period  4.00 [get_ports core_clk_b_p]
create_clock -name jesd_tx_ref_clk   -period  4.00 [get_ports ref_clk_a_p]
create_clock -name jesd_rx_ref_clk   -period  4.00 [get_ports ref_clk_b_p]

set_input_delay -clock rx_dev_clk -max 4    [get_ports sysref_b_p];
set_input_delay -clock rx_dev_clk -min 4    [get_ports sysref_b_p];

set_input_delay -clock tx_dev_clk -max 4    [get_ports sysref_a_p];
set_input_delay -clock tx_dev_clk -min 4    [get_ports sysref_a_p];

set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18}  [get_ports spi_clk]
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18}  [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN AR9  IOSTANDARD LVCMOS18}  [get_ports spi_miso]

create_clock -name spi0_clk      -period 100   [get_pins -hier */EMIOSPI0SCLKO]
